Video display systems based on spatial light modulators (SLMs) are increasingly being used as an alternative to display systems using cathode ray tubes (CRTs). SLM systems provide high resolution displays without the bulk and power consumption of CRT systems.
Digital micro-mirror devices (DMDs) are a type of SLM, and may be used for either direct-view or projection display applications. A DMD has an array of micro-mechanical display elements, each having a tiny mirror that is individually addressable by an electronic signal. Depending on the state of its addressing signal, each mirror tilts so that it either does or does not reflect light to the image plane. The mirrors may be generally referred to as "display elements", which correspond to the pixels of the image that they generate. Generally, displaying pixel data is accomplished by loading memory cells connected to the display elements. Once its memory cell is loaded, a display element is reset so that it tilts in accordance with the on or off state of the data in the memory cell. The display elements can maintain their on or off state for controlled display times.
Other SLMs operate on similar principles, with an array of display elements that may emit or reflect light simultaneously, such that a complete image is generated by addressing display elements rather than by scanning a screen. Another example of an SLM is a liquid crystal display (LCD) having individually driven display elements.
To achieve intermediate levels of illumination, between white (on) and black (off), pulse-width modulation (PWM) techniques are used. The basic PWM scheme involves first determining the rate at which images are to be presented to the viewer. This establishes a frame rate and a corresponding frame period. For example, in a standard television system, images are transmitted at 30 frames per second, and each frame lasts for approximately 33.3 milliseconds. Then, the intensity resolution for each pixel is established. In a simple example, and assuming n bits of resolution, the frame time is divided into 2.sup.n -1 equal time slices. For a 33.3 millisecond frame period and n-bit intensity values, the time slice is 33.3/(2.sup.n -1) milliseconds.
Having established these times, for each pixel of each frame, pixel intensities are quantized, such that black is 0 time slices, the intensity level represented by the LSB is 1 time slice, and maximum brightness is 2.sup.n -1 time slices. Each pixel's quantized intensity determines its on-time during a frame period. Thus, during a frame period, each pixel with a quantized value of more than 0 is on for the number of time slices that correspond to its intensity. The viewer's eye integrates the pixel brightness so that the image appears the same as if it were generated with analog levels of light.
For addressing SLMs, PWM calls for the data to be formatted into "bit-planes," each bit-plane corresponding to a bit weight of the intensity value. Thus, if each pixel's intensity is represented by an n-bit value, each frame of data has n bit-planes. Each bit-plane has a 0 or 1 value for each display element. In the simple PWM example described in the preceding paragraphs, during a frame, each bit-plane is separately loaded and the display elements are addressed according to their associated bit-plane values. For example, the bit-plane representing the LSBs of each pixel is displayed for 1 time slice, whereas the bit-plane representing the MSBs is displayed for 2n/2 time slices. Because a time slice is only 33.3/(2.sup.n -1) milliseconds, the SLM must be capable of loading the LSB bit-plane within that time. The time for loading the LSB bit-plane is the "peak data rate."
U.S. Pat. No. 5,278,652, entitled "DMD Architecture and Timing for Use in a Pulse-Width Modulated Display System," assigned to Texas Instruments Incorporated describes pulse width modulation for addressing a DMD in a DMD-based display system. It is directed to "global reset" methods, where the entire array of display elements is reset at the same time, after each is addressed with the appropriate data.
In "split reset" addressing methods, the SLM is specially configured, with its display elements are grouped into groups that are separately loaded and reset. This reduces the amount of data to be loaded during any one time. Each memory cell is shared by a display element from each group. This reduces memory hardware requirements. However, because of the shared memory cells, bit-planes must be distributed differently for each group so that loads and resets of the sharing display elements do not conflict. The split reset configuration is described in U.S. patent application Ser. No. 08/300,356, entitled "Pixel Control Circuitry for Spatial Light Modulator", assigned to Texas Instruments Incorporated.
A third type of SLM addressing is "divided reset" addressing. The display elements are divided into groups, but each display element has its own memory cell. After the memory cells of one group are loaded with their data from a bit-plane, memory cells of a next group are loaded with data from that bit-plane. This continues until all groups have been loaded with data for the same bit-plane. This phased loading is followed by a phased reset, so that all groups consecutively begin their display of the bit-plane. This method is described in U.S. patent application Ser. No. 08/721,862, entitled "Divided Reset for Addressing Spatial Light Modulator", assigned to Texas Instruments Incorporated.